SPARC

Registers

Type Names
int64 %i0, %i1, %i2, %i3, %i4, %i5, %g1, %g4, %g5, %o0, %o1, %o2, %o3, %o4, %o5, %o7, %l0, %l1, %l2, %l3, %l4, %l5, %l6, %l7
float64 %f0, %f2, %f4, %f6, %f8, %f10, %f12, %f14, %f16, %f18, %f20, %f22, %f24, %f26, %f28, %f30, %f32, %f34, %f36, %f38, %f40, %f42, %f44, %f46, %f48, %f50, %f52, %f54, %f56, %f58, %f60, %f62

Supported stack types

Type Number of bytes
stack32 4
stack64 8
stack128 16
stack256 32
stack512 64

Supported integer operations

Supported integer load/store operations

Qhasm Instruction Input Evaluated flags Output Set flags Assembly Code
r = &s int64 r, stack512 s add %fp,1967-s,r
r = *(uint64 *) (s + n) int64 s, immediate n int64 r ldx [s+n],r
r = *(uint32 *) (s + n) int64 s, immediate n int64 r lduw [s+n],r
r = *(uint8 *) (s + n) int64 s, immediate n int64 r ldub [s+n],r
r = *(int64 *) (s + n) int64 s, immediate n int64 r ldx [s+n],r
r = *(int32 *) (s + n) int64 s, immediate n int64 r ldsw [s+n],r
r = *(int8 *) (s + n) int64 s, immediate n int64 r ldsb [s+n],r
r = *(uint64 *) (s + t) int64 s, int64 t int64 r ldx [s+t],r
r = *(uint32 *) (s + t) int64 s, int64 t int64 r lduw [s+t],r
r = *(uint8 *) (s + t) int64 s, int64 t int64 r ldub [s+t],r
r = *(int64 *) (s + t) int64 s, int64 t int64 r ldx [s+t],r
r = *(int32 *) (s + t) int64 s, int64 t int64 r ldsw [s+t],r
r = *(int8 *) (s + t) int64 s, int64 t int64 r ldsb [s+t],r
r = *(swapendian uint64 *) s int64 s int64 r ldxa [s] 0x88,r
r = *(swapendian uint32 *) s int64 s int64 r lduwa [s] 0x88,r
r = *(swapendian uint8 *) s int64 s int64 r lduba [s] 0x88,r
r = *(swapendian int64 *) s int64 s int64 r ldxa [s] 0x88,r
r = *(swapendian int32 *) s int64 s int64 r ldswa [s] 0x88,r
r = *(swapendian int8 *) s int64 s int64 r ldsba [s] 0x88,r
r = s stack64 s int64 r ldx [%fp+2023-s],r
r = top32 s stack64 s int64 r ld [%fp+2023-s],r
r = bottom32 s stack64 s int64 r ld [%fp+2027-s],r
*(uint64 *) (s + n) = r int64 r, int64 s, immediate n stx r,[s+n]
*(uint32 *) (s + n) = r int64 r, int64 s, immediate n stw r,[s+n]
*(uint8 *) (s + n) = r int64 r, int64 s, immediate n stb r,[s+n]
*(int64 *) (s + n) = r int64 r, int64 s, immediate n stx r,[s+n]
*(int32 *) (s + n) = r int64 r, int64 s, immediate n stw r,[s+n]
*(int8 *) (s + n) = r int64 r, int64 s, immediate n stb r,[s+n]
*(uint64 *) (s + t) = r int64 r, int64 s, int64 t stx r,[s+t]
*(uint32 *) (s + t) = r int64 r, int64 s, int64 t stw r,[s+t]
*(uint8 *) (s + t) = r int64 r, int64 s, int64 t stb r,[s+t]
*(int64 *) (s + t) = r int64 r, int64 s, int64 t stx r,[s+t]
*(int32 *) (s + t) = r int64 r, int64 s, int64 t stw r,[s+t]
*(int8 *) (s + t) = r int64 r, int64 s, int64 t stb r,[s+t]
*(swapendian uint64 *) s = r int64 r, int64 s stxa r,[s] 0x88
*(swapendian uint32 *) s = r int64 r, int64 s stwa r,[s] 0x88
*(swapendian uint8 *) s = r int64 r, int64 s stba r,[s] 0x88
*(swapendian int64 *) s = r int64 r, int64 s stxa r,[s] 0x88
*(swapendian int32 *) s = r int64 r, int64 s stwa r,[s] 0x88
*(swapendian int8 *) s = r int64 r, int64 s stba r,[s] 0x88
r = s int64 s stack64 r stx s,[%fp+2023-r]
round *(uint32 *) (s + n) int64 s, immediate n ld [s+n],%fsr

Supported integer arithmetic operations

Qhasm Instruction Input Evaluated flags Output Set flags Assembly Code
r = s int64 s int64 r add %g0,s,r
r &= t int64 r, int64 t int64 r and r,t,r
r = s & t int64 s, int64 t int64 r and s,t,r
r &= n int64 r, immediate n int64 r and r,n,r
r &= ~t int64 r, int64 t int64 r andn r,t,r
r += t int64 r, int64 t int64 r add r,t,r
r += t int64 r, int64 t int64 r unsigned>, unsigned<, =, carry32 addcc r,t,r
r = s + t int64 s, int64 t int64 r add s,t,r
r = s + t int64 s, int64 t int64 r unsigned>, unsigned<, =, carry32 addcc s,t,r
r += t + carry32 int64 r, int64 t carry32 int64 r unsigned>, unsigned<, =, carry32 addccc r,t,r
r = s + t + carry32 int64 s, int64 t carry32 int64 r unsigned>, unsigned<, =, carry32 addccc s,t,r
r += n int64 r, immediate n int64 r add r,n,r
r += n int64 r, immediate n int64 r unsigned>, unsigned<, =, carry32 addcc r,n,r
r = s + n int64 s, immediate n int64 r add s,n,r
r = s + n int64 s, immediate n int64 r unsigned>, unsigned<, =, carry32 addcc s,n,r
r += n + carry32 int64 r, immediate n carry32 int64 r unsigned>, unsigned<, =, carry32 addccc r,n,r
r = s + n + carry32 int64 s, immediate n carry32 int64 r unsigned>, unsigned<, =, carry32 addccc s,n,r
r -= t int64 r, int64 t int64 r sub r,t,r
r -= t int64 r, int64 t int64 r unsigned>, unsigned<, =, carry32 subcc r,t,r
r - t int64 r, int64 t unsigned>, unsigned<, =, carry32 subcc r,t,%g0
r = s - t int64 s, int64 t int64 r sub s,t,r
r = s - t int64 s, int64 t int64 r unsigned>, unsigned<, =, carry32 subcc s,t,r
r = -n immediate n int64 r sub %g0,n,r
r -= n int64 r, immediate n int64 r sub r,n,r
r -= n int64 r, immediate n int64 r unsigned>, unsigned<, =, carry32 subcc r,n,r
r - n int64 r, immediate n unsigned>, unsigned<, =, carry32 subcc r,n,%g0
r = s - n int64 s, immediate n int64 r sub s,n,r
(int32) r <<= n int64 r, immediate n int64 r sll r,n,r
(int64) r <<= n int64 r, immediate n int64 r sllx r,n,r
(uint32) r <<= n int64 r, immediate n int64 r sll r,n,r
(uint64) r <<= n int64 r, immediate n int64 r sllx r,n,r
r <<= n int64 r, immediate n int64 r sllx r,n,r
r = (int32) s << n int64 s, immediate n int64 r sll s,n,r
r = (int64) s << n int64 s, immediate n int64 r sllx s,n,r
r = (uint32) s << n int64 s, immediate n int64 r sll s,n,r
r = (uint64) s << n int64 s, immediate n int64 r sllx s,n,r
r = s << n int64 s, immediate n int64 r sllx s,n,r
(int32) r >>= n int64 r, immediate n int64 r sra r,n,r
(int64) r >>= n int64 r, immediate n int64 r srax r,n,r
(uint32) r >>= n int64 r, immediate n int64 r srl r,n,r
(uint64) r >>= n int64 r, immediate n int64 r srlx r,n,r
r = (int32) s >> n int64 s, immediate n int64 r sra s,n,r
r = (int64) s >> n int64 s, immediate n int64 r srax s,n,r
r = (uint32) s >> n int64 s, immediate n int64 r srl s,n,r
r = (uint64) s >> n int64 s, immediate n int64 r srlx s,n,r
r ^= t int64 r, int64 t int64 r xor r,t,r
r = s ^ t int64 s, int64 t int64 r xor s,t,r
r ^= n int64 r, immediate n int64 r xor r,n,r
r = n immediate n int64 r add %g0,n,r
r = n & 0xfffffc00 immediate n int64 r sethi %lm(n),r
r = (n & 0xfffffc0000000000) >> 32 immediate n int64 r sethi %hh(n),r
r |= t int64 r, int64 t int64 r or r,t,r
r = s | t int64 s, int64 t int64 r or s,t,r
r |= n int64 r, immediate n int64 r or r,n,r
r |= n & 0x3ff int64 r, immediate n int64 r or r,%lo(n),r
r |= (n & 0x3ff00000000) >> 32 int64 r, immediate n int64 r or r,%hm(n),r
r = ~t int64 t int64 r not t,r

Supported floating point operations

Supported floating point load/store operations

Qhasm Instruction Input Evaluated flags Output Set flags Assembly Code
r = s stack64 s float64 r ldd [%fp+2023-s],r
r = *(float64 *) (s + n) int64 s, immediate n float64 r ldd [s+n],r
r = s float64 s stack64 r std s,[%fp+2023-r]
*(float64 *) (s + n) = r float64 r, int64 s, immediate n std r,[s+n]

Supported floating point arithmetic operations

Qhasm Instruction Input Evaluated flags Output Set flags Assembly Code
r = s * t float64 s, float64 t float64 r fmuld s,t,r
r *= t float64 r, float64 t float64 r fmuld r,t,r
r = s + t float64 s, float64 t float64 r faddd s,t,r
r += t float64 r, float64 t float64 r faddd r,t,r
r = s - t float64 s, float64 t float64 r fsubd s,t,r
r -= t float64 r, float64 t float64 r fsubd r,t,r

Supported misc operations

Supported misc misc operations

Qhasm Instruction Input Evaluated flags Output Set flags Assembly Code
nop nop
f# immediate f ._f!:

Supported branch operations

Supported branch conditional operations

Qhasm Instruction Input Evaluated flags Output Set flags Assembly Code
goto f if = immediate f = nop
goto f if != immediate f = nop
goto f if unsigned> immediate f unsigned> nop
goto f if !unsigned> immediate f unsigned> nop
goto f if unsigned< immediate f unsigned< nop
goto f if !unsigned< immediate f unsigned< nop

Supported branch unconditional operations

Qhasm Instruction Input Evaluated flags Output Set flags Assembly Code
goto f immediate f nop

Supported declaration operations

Supported declaration misc operations

Qhasm Instruction Input Evaluated flags Output Set flags Assembly Code
float64 r
int64 r
stack128 r
stack256 r
stack512 r
stack64 r